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never stop thinking. HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/l3.6] HYB25D128323C[-4.5/l4.5] HYB25D128323C-5 128 mbit ddr sgram data sheet, v1.7, july 2003 memory products
edition 2003-07 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/l3.6] HYB25D128323C[-4.5/l4.5] HYB25D128323C-5 128 mbit ddr sgram data sheet, v1.7, july 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/l3. 6], HYB25D128323C[-4.5/l4.5], HYB25D128323C-5 revision history: v1.7 2003-07 previous version: v1.51 2002-07 page subjects (major changes since last revision) all new data sheet template 43 ac operation conditions : input slew rate added 46 timing parameters for speed sorts ?3, ?3.3, ?3.6, ?4.5, and ?5 : write dqs high/low added 48 timing parameters for speed sorts l3.6 and l4.5 : write dqs high/low added previous version: v1.51 2002-07 9 , 13 , 42 , 46 , 48 extended v dd range for ?3.6 and l3.6 we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 extended mode register setup (emrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 signal and timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 special signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.1 clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.2 command inputs and addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.3 data strobe and data mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.3.1 operation at burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.3.2 operation at burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 description of timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.2 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.3 extended mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.4 bank activation command (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.5 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.6 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.7 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.8 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.9 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.10 burst read operation: (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.11 burst write operation (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.12 burst stop command (bst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.13 data mask (dmx) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.14 autoprecharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.15 read with autoprecharge (reada) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.16 write with autoprecharge (writea) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 burst interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6.1 read interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6.2 read interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.3 read interrupted by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.4 write interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.5 write interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.6 write interrupted by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 operations and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.8 function truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9 ddr sgram simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table of contents
data sheet 6 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] figure 1 ball out 128mbit ddr sgram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3 mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4 extended mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 command and address signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6 dqs timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 dqs and dm timing at write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8 dqs pre/postamble at write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 activate to read or write command timing (one bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 activate bank a to activate bank b timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 precharge command timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14 self refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15 autorefresh timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16 power down mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17 burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18 burst write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19 burst stop for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20 data mask timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 21 read burst with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22 read concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 23 write burst with auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 24 read interrupted by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 25 read interrupted by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 26 read interrupted by precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 27 write interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 28 write interrupted by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 29 write interrupted by precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 30 ddr sgram simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 31 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 32 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 list of figures
data sheet 7 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32]
data sheet 8 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 signal and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 io driver strength and interface settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4 mapping of dqsx and dmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5 precharge control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6 burst mode and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7 concurrent read auto precharge support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8 concurrent write auto precharge support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9 command overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11 function truth table i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12 function truth table for cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 14 power & dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15 ac operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 17 timing parameters for speed sorts ?3, ?3.3, ?3.6, ?4.5, and ?5 . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18 timing parameters for speed sorts l3.6 and l4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19 HYB25D128323C?3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20 HYB25D128323C?3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 21 HYB25D128323C?3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22 HYB25D128323C?4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23 HYB25D128323C?5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24 HYB25D128323Cl3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 25 HYB25D128323Cl4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 26 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of tables
data sheet 9 v1.7, 2003-07 128 mbit ddr sgram HYB25D128323C[-3/-3.3] HYB25D128323C[-3.6/l3.6] HYB25D128323C[-4.5/l4.5] HYB25D128323C-5 1overview 1.1 features maximum clock frequency up to 333 mhz maximum data rate up to 666 mbps/pin data transfer on both edges of clock programmable cas latency of 2, 3 and 4 clocks programmable burst length of 2, 4 and 8 integrated dll to align dqs and dq transitions with clk data transfer signals are synchronized with byte wise bidirectional data strobe data strobe signal edge-aligned with data for read operations data strobe signal center aligned with data for write operations differential clock in puts (clk and clk ) data mask for masking write data, one dm per byte organization 1024k 32 4 banks 4096 rows and 256 columns per bank 4k refresh (32ms) refresh interval 7.8 sec autorefresh and self refresh available standard jedec tf-xbga 128 package self-mirrored, symmetrical ball out matched impedance mode interface (z 0 =60 ? ) sstl-2 jedec weak mode interface (z 0 =34 ? ) io voltage v ddq =2.5v v dd power supply memory core: ? speed sorts ?3 and ?3.3: 2.5 v < v dd < 2.9 v ? speed sorts l4.5, ?4.5, and ?5: v dd =2.5v ? speed sorts l3.6 and ?3.6 support both v dd modes 1.2 description the infineon 128mbit ddr sgram is a ultra high perfor mance graphics memory device, designed to meet all requirements for high bandwidth intensiv e applications like pc graphics systems. the 128mbit ddr sgram uses a double-data-rate dram architecture organized as 4 banks 4096 rows 256 columns 32 bits. the double-data-rate architecture is essent ially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access to the ddr table 1 performance part number speed code ? 3 ? 3.3 ? 3.6 ? 4.5 ? 5.0 l3.6 l4.5 unit cas latency 4 t ck4min. 3 3.3 3.6 4.5 5.0 3.6 4.5 ns f ck4max. 333 300 278 222 200 278 222 mhz cas latency 3 t ck3min. 4.0 4.0 4.2 4.5 5.0 4.2 4.5 ns f ck3max. 250 250 238 222 200 238 222 mhz data out window t qh 1.05 1.15 1.26 1.58 1.75 1.26 1.58 ns dqs-dq skew t dqsq 0.30 0.30 0.33 0.45 0.5 0.33 0.45 ns
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] overview data sheet 10 v1.7, 2003-07 sgram consists of a single 64-bit wide, one clock cycle data transfer at the internal dram core and two corresponding 32-bit wide, one-half clock cycle data transfers at the i/o pins. the result is a data rate of 666 mbits / sec per pin. the external data interface is 32 bit wi de and achieves at 333 mhz system clock a peak bandwidth of 2.66 gigabytes/sec. the device is supplied with 2.5 v resp. within the range of 2.5 v - 2.9 v for the memory core and 2.5 v for the output drivers. two drivers strengths are available: 2.5 v matched impedance mode and sstl2 weak mode. the ?matched impedance mode? interface is optimized for high frequency digital data transfers and matches the impedance of graphics board systems (60ohm). auto refresh and self refresh operations are both supported. a standard jedec tf-xbga 128 package is used which enab les ultra high speed clock and data transfer rates. the signals are mapped symmetrically to the balls in order to enable mirrored mounting in application. the chip is fabricated in infineon technologies advanced 256m process technology.
data sheet 11 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] pin configuration 2 pin configuration figure 1 ball out 128mbit ddr sgram note: the inner matrix of 4 4 balls will be used as thermal v ss contacts ncluding the thermal v ss contacts, the total amount of balls is 144 128 ball xbga 4 banks x 4096 rows x 256 columns x 32 bits 123 12 10 11 d b c h e f g m j k l v ssq a v ssq 9 78 6 45 dq 4 dqs 0 dq 3 dm 0 v ddq dq 2 dq 0 dq 31 dq 29 dq 28 dm 3 dqs 3 nc v ddq dq 1 v ddq v ddq dq 30 v ddq nc v ddq dq 26 dq 27 dq 6 dq 5 v ssq v ssq v ssq v dd v dd v ssq v ssq v ssq dq 24 dq 25 v ddq v dd v ss v ssq v ss v ss v ssq v ss v dd dq 7 v ddq dq 17 dq 16 v ddq v ssq v ssq dq 15 v ddq dq 14 dq 12 dq 13 v ddq dq 11 v ssq dq 8 v ssq dq 9 nc dm 1 dqs 1 dq 10 v ref v ddq v ssq dq 18 dq 19 v ddq v ssq v ssq dq 20 dm 2 nc dqs 2 dq 21 dq 22 v ddq v ssq dq 23 v ddq v ssq v ss v ss a 6 v ssq cke v ddq nc clk nc v dd a 5 a 9 v ss rfu a 10 v dd v dd a 2 v ss ras# we# v dd cas# cs# ba 1 ba 0 nc nc nc a 1 a 3 a 0 a 11 a 4 rfu a 7 clk# mcl a8/ap v ss v ss top view
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] pin configuration data sheet 12 v1.7, 2003-07 table 2 signal and pin description pin io type detailed function clk, clk input clock : clk and clk# are differential clock inputs. all address and command inputs are latched on the crossing of the positive edge of clk and the negative edge of clk . output data (dq?s and dqs) is referenced to the crossing of clk and clk . cke input clock enable : cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power- down and self refresh operations (a ll banks idle), or active power-down (row active in any bank). cke is synchr onous for power-down entry and exit, and for self refresh entry. cke is asynch ronous for self-refresh exit. cke must be maintained high trough out read and write accesses. input buffers (excluding clk, clk ) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl2 input but will detect an lvcmos low level after vdd is applied. cs input chip select : cs# enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands are ignored, but internal operations continue. cs# is considered part of the command code. ras , cas , we input command inputs : cas , ras , and we (along with cs ) define the command to be executed. ba1, ba0 input bank address inputs : ba0 and ba1 select to which internal bank an active, read, write, or precharge command is being applied. they also define which mode register (mode register or extended mode register) is loaded during a mode register set command. a11.. a0 input address inputs : during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11). during a read or write command cycle, a0-a7 defines the column address (ca0-ca7). in addition to the column address, a8/ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a8 is high, the acti ve bank is precharged. if a8 is low, the autoprecharge function is disabled. during a precharge command cycle, a8/ap is used to determin e, which bank(s) will be precharged. if a8/ ap is high, all four banks will be precharged re gardless of the state of ba0 and ba1. if a8/ap is low, ba0 and ba1 define the bank to be precharged. the address inputs also provide the op-code during a mode register set command. dqs3.. dqs0 i/o data strobes : the dqsx are the bidirectional strobe signals. at read cycles, the dqsx signals are generated by the sgram and are edge-aligned to the data. at write cycles, the dqs signals are generated by the controller. the ri sing or falling edge indicates the center of the data valid window. before and after a transfer cycle, dqsx enters a preamble and a postamble state. the dqsx signals are mapped to the following data bytes: dqs0 to dq0.. dq7, dqs1 to dq8.. dq15, dqs2 to dq16..dq23, dqs3 to dq24.. dq31. dq31.. dq0 i/o data input/output : the dqx signals form the 32 bit wide data bus. at read cycles the pins are outputs and during write cycles inputs. the data is transferred at both edges of the dqsx signals.
data sheet 13 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] pin configuration dm3.. dm0 input input data mask : the dm signals are input mask signal for write data. they mask off a complete byte on the data bus. dmx = 1 prevents the corresponding byte from being written. dm3 corresponds to dq31..dq24, dm2 to dq23..dq16, dm1 to dq15..dq8, dm0 to dq7..dq0. dm signals are sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. v ref input voltage reference : v ref is the reference voltage input signal. v dd, v ss supply power supply : power and ground for the internal logic. v dd = 2.5 v 5% for l4.5, ?4.5, and -5 2.5 v ? 5% < v dd < 2.9 v for ?3.6 and l3.6 2.5 v < v dd < 2.9 v for ?3 and ?3.3 v ddq, v ssq supply io power supply : isolated power and ground for the output buffers to provide improved noise immunity. v ddq = 2.5v 5% nc, rfu ? please do not connect no conn ect, reserved for future use pins. mcl ? must be connected to low table 2 signal and pin description (cont?d) pin io type detailed function
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] pin configuration data sheet 14 v1.7, 2003-07 figure 2 functional blocks column address counter column address buffer refresh counter column decoder sense amplifiers and data bus buffer memory array bank 0 4096 x 256 x 32 bit control logic & timing generator dq7-dq0 dq15-dq8 dq23-dq16 dq31-dq24 row addresses a11-a0, ba1-ba0 column addresses a7-a0, ap row address buffer column decoder sense amplifiers and data bus buffer column decoder sense amplifiers and data bus buffer column decoder sense amplifiers and data bus buffer memory array 4096 x 256 x 32 bit memory array 4096 x 256 x 32 bit memory array 4096 x 256 x 32 bit bank 1 bank 2 bank 3 row decoder row decoder row decoder row decoder input buffers output buffers data data data data dqs3 dqs2 dqs1 dqs0 dm3 dm2 dm1 dm0 clk clk# cke cs# ras# cas# we# v ref
data sheet 15 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set 3register set 3.1 mode register the mode register stores the data for controlling the various operating modes of the ddr sg ram. it programs cas latency, addressing mode, burst length, test mode, dll on and various vendor specific options. the default value of the mode register is not defined. therefore the mode register must be written after power up to operate the ddr sgram. the ddr sgram should be activated with cke already high prior to writing into the mode register. the mode register is written by using the mr s command. the state of the address signals registered in the same cycle as mrs command is written in the mode register. the value can be changed as long as all banks are in the idle state. the mode register is divided into various fields dependi ng on functionality. the burst length uses a2.. a0, cas latency (read latency from column address) uses a6.. a4. a7 is used for test mode, a8 is used for dll reset. a7, a8 and ba1 must be set to low for normal ddr sgram opera tion. a9.. a11 is reserved fo r future use. ba0 selects extended mode register setup operation when set to 1. refer to the table for specific codes for various burst length, addressing modes and cas latencies. figure 3 mode register bitmap ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 dll rfu tm cas latency bt burst length a7 0 1 mode normal testmode testmode a8 0 1 dll reset yes dll reset no a3 0 1 type sequential reserved burst type address bus mode register latency 2 a6 a5 a4 all other reserved 3 0 0 0 1 1 cas latency length 2 a2 a1 a0 4 8 0 0 0 0 1 1 1 1 sequential interleave 0 8 4 2 burst length all other reserved ba0 0 1 accessed register extend. mode reg. extended mode register access mode register 00 a11 a10 rfu rfu 1 4 1 0 0
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 16 v1.7, 2003-07 3.2 extended mode register setup (emrs) the extended mode register is responsible for enabling / disabling the dll in the HYB25D128323C and for selecting the interface type for the ios and input pins. the extended mode register can be programmed by performing a normal mode register setup operation and setting the ba0 bit to high. all other bits of the emrs register are reserved and should be set to low. the bit a0 enables / disables the dll. the bits a1 and a6 set the driver strength of the ios. for detailed explanation, refer to the following table. note: the combination a6=0 and a1 =0 defines sstl-2 strong mode in 32m ddr sgram which is not supported in this device. figure 4 extended mode register bitmap 3.3 signal and ti ming description 3.3.1 general description the 128mbit ddr sgram is a 16mbyte sy nchronous graphics dram. it consists of four banks. each bank is organized as 4096 rows 256 columns 32 bits. read and write accesses are burst oriented. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. ba1 and ba0 select the bank, address bits a11.. a0 select the row. address bits a7.. a0 registered coincident with the read or write command are used to select the starting column location fo r the burst access. the regular single data rate sgram re ad and write cycles only use the risi ng edge of the external clock input. for the ddr sgram, the special signals dqsx (data strobe) are used to mark the data valid window. during table 3 io driver strength and interface settings a6 a1 drive strength strength/ impedance io power supply vddq comment 0 0 sstl-2 weak 60% / 34ohm 2.5v replacement for strong mode 0 1 sstl-2 weak 60% / 34ohm 2.5v ? 10rfurfurfudo not use 1 1 matched impedance mode 30% / 60ohm 2.5v output driver matches line impedance dll rfu must be set to "0" a0 0 1 dll enable enable disable ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 0 1 accessed register extend. mode reg. extended mode register access mode register 0 address bus extended mode register 1 ds0 a1 0 1 drive strength a11 a10 ds1 a6 0 0 0rfu 1 matched impedance 2.5v 1 1 rfu must be set to "0" sstl ii-weak mode sstl ii-weak mode
data sheet 17 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set read bursts, the data valid window coincides with the high or low level of the dqsx signals. during write bursts, the dqsx signal marks the center of the valid data window. data is availa ble at every rising and falling edge of dqsx, therefore the data transfer rate is doubled. for read accesses, the dqsx signals are aligned to the clock signal clk. 3.4 special signal description 3.4.1 clock signal the ddr sgram operates with a differential clock (clk and clk#) input. clk is used to latch the address and command signals. data input and dmx signals are latched with dqsx. the ddr sgram implements a delay locked loop circuit (dll) which tracks both edges of the clk input signal and aligns the dqs output edges with the clk input edges. the minimum and maximum clock cycle time is defined by t ck . the maximum value for t ck is defined to provide a lower bound for the operation frequency of the internal dll circuit. the minimum and maximum clock duty cycle are specified using the minimum clock high time t ch and the minimum clock low time t cl respectively. the internal dll circuit requ ires additional 200 clock cycles after dll reset for internal clock stabilization. 3.4.2 command i nputs and addresses like single data rate sgrams, each combination of ras#, cas# and we# input in conjunction with cs# input at a rising edge of the clock determines a ddr sgram command. figure 5 command and address signal timing 3.4.3 data strobe and data mask 3.4.3.1 operation at burst reads the data strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. the data strobe signal goes t rpre clock cycle low before data is driven by the ddr sgram and then toggles low to high and high to low till the end of the burst. the cas la tency is specified to the firs t low to high transition. the edges of the output data signals and the edges of the da ta strobe signals during a read are nominally coincident with edges of the input clock. the tolerance of these edges is specified by the parameters t ac and t dqsck and is referenced to the crossing point of the clk and clk# signal. the t dqsq timing parameter describes the skew between the data strobe edge and the output data edge. the following table summarizes the mapping of dqsx and dmx signals to the data bus. valid valid clk, clk# address, cs#, ras#, cas#, we#, cke vih vtt vil vih vil t is t ih
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 18 v1.7, 2003-07 the minimum time during which the output data is valid is critical for the rece iving device. this also applies to the data strobe dqs during a read since it is tightly coupled to the output data. the parameters t qh and t dqsq define the minimum output data valid window. prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit from hi-z to a valid logic low. this is referred to as the data strobe ?read preamble? t rpre . once the burst of read data is concluded, given that no su bsequent burst read operation is initiated, the data strobe signals transit from a valid logic low to hi-z. this is referred to as the data strobe ?read postamble? t rpst . figure 6 dqs timing for read 3.4.3.2 operation at burst write during a write burst, control of the data strobe is driven by the memory controller. the dqsx signals are nominally centered with respect to data and data mask. the tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the setup and hold time parameters of data ( t qdqss & t qdqsh ) and data mask ( t dmdqss & t dmdqsh ). the input data is masked in the same cycle when the corresponding dmx signal is high (i.e. the dmx mask to write latency is zero.) table 4 mapping of dqsx and dmx data strobe signal data mask signal controlled data bus dqs0 dm0 dq7 .. dq0 dqs1 dm1 dq8 .. dq15 dqs2 dm2 dq16 .. dq23 dqs3 dm3 dq24 .. dq31 dqx clk, clk# dqs "preamble" "postamble" vih vtt vil t rpre t rpst d d+1 d+2 d+3 vih vtt vil t dqsq t ac t0 t1 t2 t3 t4 vih vil t ch t cl t ck t dqsck t hp t qh t qhs
data sheet 19 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 7 dqs and dm timing at write prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal (dqsx) transits from hi-z to a valid logic low. this is referred to as the data strobe ?write preamble?. once the burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal (dqsx) transits from a valid logic lo w to hi-z. this is referred to as the data strobe ?write postamble?, t wpst . for ddr sgram, data is written with a delay which is defined by the parameter t dqss (ddr write latency). this is different than the single data rate sgram where data is written in the same cycle as the write command is issued. figure 8 dqs pre/postamble at write q+2 q+4 q+1 dqsx vih vtt vil dmx vih vtt vil t dmdqss t dmdqss t dmdqsh t dmdqsh t qdqsh t qdqsh dqx qq+3 vih vtt vil t qdqss t qdqss input data masked clk, clk# vih vil wr dqsx vih vtt vil dqx q q+1 q+2 q+3 vih vtt vil t dqss t wpreh t wpres t wpst "preamble" "postamble"
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 20 v1.7, 2003-07 3.5 description of timings 3.5.1 power-up sequence the following sequence is highly recommended for power-up: 1. apply power and start clock. maintain cke=l and the other pins are in nop conditions at the input 2. apply v dd before or at the same time as v ddq , apply v ddq before or at the same time as v ref & v tt 3. start clock, maintain st able conditions for 200 s min. 4. apply nop and set cke to high 5. apply a precharge all command 6. issue emrs (extended mode register set) command to enable the dll 7. issue a mode register set command for ?dll reset?. 200 cycles of clock input are required to lock the dll. 8. issue precharge commands for all banks of the device. 9. issue two or more auto-refresh commands. 10. issue a mode register set command. (this step may also be taken as step 6) figure 9 power-up sequence 3.5.2 mode register set timing the ddr sgram should be activated wit h cke already high prior to writing into the mode register. two clock cycles are required to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. figure 10 mode register set timing 3.5.3 extended mode re gister set timing the timing of the extended mode register setup operati on is equivalent to the mode register setup timing. clock command emrs prea dll prea aref aref mrs any comm. t mrd 200 clock min. t rp t rfc t rfc t mrd t rp nop 2 clock min. reset clk command t rp t mrd nop prea nop mrs nop comm. any nop
data sheet 21 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set 3.5.4 bank activatio n command (act) the bank activation command is initiate d by issuing an act command at the rising edge of the clock. the ddr sgram has four independent banks which are selected by the two bank select addr esses (ba0, ba1). the bank activation command must be applied before any read or write operation can be executed. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time ( t rcddc min . for read commands and t rcdwr min. for write commands). once a bank has been activated, it must be precharged before another bank activate command can be applied to the same bank. the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank activation delay time ( t rrd min). figure 11 activate to read or write command timing (one bank) figure 12 activate bank a to activate bank b timing 3.5.5 precharge command this command is used to precharge or close a bank that has been activated. precharge is initiated by issuing a precharge command at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank addresses ba0 and ba1 select the bank to be precharged. after a precharge command, the analog delay t rp has to be met until a new activate command can be initiated to the same bank. clk command t rcdwr for write bank a act t rcdrd for read t rc addresses row add. read write or bank a col. add. bank a pre nop act bank a row add. clk command bank b act t rrd addresses row add. nop act bank a row add.
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 22 v1.7, 2003-07 figure 13 precharge command timing 3.5.6 self refresh the self refresh mode can be used to retain the data in the ddr sgram if the chip is powered down. to set the ddr sgram into a self refreshing mo de, a self refresh command must be issued and cke held low at the rising edge of the clock. once the self refresh command is in itiated, cke must stay low to keep the device in self refresh mode. during the self refresh mode, all of the external control signals are disabled except cke. the clock is internally disabled during self re fresh operation to reduce power. an internal timing generator guarantees the self refreshing of the memory content. to exit the self refresh mode, a stable external clock is needed for the dll before returning cke high. after the power down exit time( t pdex ), a deselect or nop command is issued and cke is held high for longer than t srex in order to lock the dll. table 5 precharge control a8/ap ba1 ba0 precharged 000bank a only 001bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks clk command act t rc addresses bank a pre nop act bank a row add t ras t rp nop bank a row add
data sheet 23 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 14 self refresh timing 3.5.7 auto refresh the auto refresh function is initiated by issuing an auto refresh command at the rising edge of the clock. all banks must be precharged and idle before the auto refresh command is applied. no control of the external address pins is required once this cycle has started. all necessary addresses are generated in the device itself. when the refresh cycle has completed, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refres h command must be greater than or equal to the t rfc (min). figure 15 autorefresh timing 3.5.8 power down mode the power down mode is en tered when cke is set low and exited when cke is set high. the cke signal is sampled at the rising edge of the clock. once the power down mode is initiated, all of the receiver circuits except clk, cke and dll circuits are gated off to reduce power consumption. all banks can be set to idle state or stay activate during power down mode, but burst activity may not be performed. after exiting from power down mode, at least one clock cycle of command delay must be inserted before starting a new command. during power down mode, refresh operations cannot be performed; therefore, the device cannot remain in power down mode longer than the refresh period ( t ref ) of the device. clk command nop t srex cke self refresh nop desel nop desel nop desel nop desel any comm. clk command nop t rfc cke pre- charge auto refresh command t rp nop command is autorefresh or act
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 24 v1.7, 2003-07 figure 16 power down mode timing 3.5.9 burst mode operation burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory (read cycle). the burst length is programmable and set by address bits a0 - a3 during the mode register setup command. the burst length controls the number of words that will be output after a read command or the number of words to be input after a write command. one word is 32 bits wide. the sequential burst length can be set to 2, 4 or 8 data words. 3.5.10 burst read op eration: (read) the burst read operation is initiated by issuing a read command at the rising edge of the clock after t rcd from the bank activation. the address inputs (a7.. a0) determi ne the starting address for the burst. the burst length (2, 4 or 8) must be defined in the mode register. the first data after the read command is available depending on the cas latency. the subsequ ent data is clocked out on the rising and falling edge of dqsx until the burst is completed. the dqsx signal is generated by the ddr sgram dur ing burst read operations. table 6 burst mode and sequence burst length starting column address order of access within a burst a2 a1 a0 type = sequential 200 - 1 11 - 0 4 0 0 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 0 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 clk command pre t pdex cke nop any command power down mode entry nop nop desel power down mode exit nop desel
data sheet 25 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 17 burst read operation 3.5.11 burst write operation (write) the burst write is initiated by issuing a write command at the rising edge of the clock. the address inputs (a7.. a0) determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the first rising edge of dqsx following the write comm and. the time between the write command and the first corresponding edge of the data strobe is t dqss . the remaining data inputs must be supplied on each subsequent rising and falling edge of th e data strobe until the burst length is completed. when the burst has been finished, any additional data supplied to the dq pins will be ignored. clk read dqsx dqx command cl = 2 nop nop nop nop nop nop read preamble nop d-out 0 d-out 1 d-out 2 d-out 3 burst length = 4 dqsx dqx d-out 0 d-out 1 d-out 2 d-out 3 read postamble cas latency = 2 cas latency = 3 cl = 3 read preamble read postamble dqsx dqx cas latency = 4 cl = 4 d-out 0 d-out 1 d-out 2 d-out 3 read preamble read postamble
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 26 v1.7, 2003-07 figure 18 burst write operation 3.5.12 burst stop command (bst) a burst stop is initiated by issuing a burst stop command at the rising edge of the clock. the burst stop command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has been completed. when the burst stop command is issued during a burst read cycle, read data and dqsx go to a high impedance state after a delay which is equal to t he cas latency set in the mode register. the burst stop latency is equal to the cas latency cl.the burst stop command is not supported during a write burst operation. burst stop is also illegal du ring read with auto-precharge. clk write dqsx dqx data-in 0 t dqss t wpreh t wpres t wpst burst length = 4 nop nop nop data-in 1 data-in 2 data-in 3
data sheet 27 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 19 burst stop for read 3.5.13 data ma sk (dmx) function the ddr sgram has a data mask function that can be used only during write cycles. when the data mask is activated (dmx high) during burst write, the write operatio n is masked immediately. the dmx to data-mask latency is zero. dmx can be issued at the ri sing or falling edge of data strobe. clk read dqsx dqx command cl = 2 bst nop nop nop nop nop nop d-out 0 d-out 1 burst length = 4 dqsx dqx d-out 0 d-out 1 cas latency = 2 cas latency = 3 cl = 3 burst stop latency = 2 burst stop latency = 3 dqsx dqx cas latency = 4 d-out 0 d-out 1 burst stop latency = 4
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 28 v1.7, 2003-07 figure 20 data mask timing 3.5.14 autoprechar ge operation the autoprecharge command is issued by setting column address a8 high when a read or a write command is asserted to the ddr sgram. if a8 is low when read or write command is issued, a normal read or write burst operation is executed and the bank remains active at the end of the burst sequence. when the auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the read or write cycle after t ras(min.) is satisfied. 3.5.15 read with au toprecharge (reada) if a read with auto-precharge comm and is initiated, the ddr sgram automatically enters the precharge operation bl/2 clock cycles after the reada command and t ras(min.) is satisfied. if t ras(min.) has not been satisfied yet, an internal in terlock will delay the precharge ope ration until it is satisfied. once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time ( t rp ) has been satisfied. d-in 2 clk write dqsx dqx d-in 0 command dmx nop nop nop nop nop nop d-in 1 d-in 3 nop burst length = 8 d-in 6 d-in 4 d-in 5 d-in 7 data is masked out
data sheet 29 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 21 read burst with autoprecharge clk reada dqsx dqx command cl = 2 nop nop nop nop nop act d-out 0 d-out 1 d-out 2 d-out 3 burst length = 4 dqsx dqx d-out 0 d-out 1 d-out 2 d-out 3 cas latency = 2 cas latency = 3 cl = 3 bank can be activated after completion of precharge dqsx dqx d-out 0 d-out 1 d-out 2 d-out 3 cas latency = 4 begin of autoprecharge bl / 2 t rp nop cl = 4
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 30 v1.7, 2003-07 figure 22 read concurrent auto precharge note: this table is for the case of burst length = 4, cas latency =3 and t wr =2 clocks when read with auto precharge is asserted, new commands can be asserted at t4,t5 and t6 as shown in table 7 . an interrupt of a running read burst with auto precharge i.e. at t4 and t5 to the same bank with another read+ap command is allowed, it will ext end the begin of the inte rnal precharge operation to the last read+ap command. interrupts of a running read burst with auto precharge i.e. at t4 are not allowed when doing concurrent command to another active bank. activate or precharge commands to another bank are always possible while a read with auto precharge operation is in progress. 3.5.16 write with autoprecharge (writea) if a8 is high when a write command is issued, the writ e with auto-precharge function is performed. the internal precharge begins after the write recovery time t wr and t ras(min.) are satisfied. if a write with auto precharge co mmand is initiated, the ddr sgram automatically ent ers the precharge operation at the first rising edge of clk after the last valid edge of dqs (completion of the burst) plus the write recovery time t wr . once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time ( t rp ) has been satisfied. if t ras(min.) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied. table 7 concurrent read auto precharge support asserted command for same bank for different bank t4 t5 t6 t4 t5 t6 read no no no no yes yes read+ap yes yes no no yes yes activate no no no yes yes yes precharge yes yes no yes yes yes clk bank a activate command nop nop read a + ap nop nop burst length = 4 dqsx dqx d-out 0 d-out 1 d-out 2 d-out 3 cas latency = 3 cl = 3 begin of auto precharge bl / 2 nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t rcd(min) t ras(min) t rp
data sheet 31 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 23 write burst with auto precharge note: t wr starts at the first rising edge of clock after the last valid edge of the 4 dqsx. when write with auto precharge is asserted, new commands can be asserted at t3.. t8 as shown in table 8 . an interrupt of a running write burst with auto precharge i.e. at t3 to the same bank with another write+ap command is allowed as long as the burst is running, it will extend the be gin of the internal precharge ope ration to the last write+ap command. interrupts of a running write burst with auto precharge i.e. at t3 are not allowed when doing concurrent write?s to another active bank. consecutive write or write+ap bursts (t4.. t7) to other open banks are possible. activate or pre charge commands to another bank are always possible while a write with auto precharge operation is in progress. 3.6 burst interruption 3.6.1 read interrupted by a read a burst read can be interrupted before completion of the burst by a new read command given to any bank. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the table 8 concurrent write auto precharge support asserted command for same bank for different bank t3 t4 t5 t6 t7 t8 t3 t4 t5 t6 t7 write nononononononoyesyesyesyes write+ap yes no no no no no no yes yes yes yes read no no no no no no no no no no yes read+ap nonononononononononoyes activate no no no no no no yes yes yes yes yes precharge no no no no no no yes yes yes yes yes write a + ap clk bank a activate command nop nop nop nop burst length = 4 dqsx dqx d-in 0 d-in 1 d-in 2 d-in 3 begin of auto precharge bl / 2 nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t ras(min) t rp t wr
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 32 v1.7, 2003-07 interrupting read command is satisfied. at this point, th e data from the interrupting read command appears. read to read interval (cas#(a) to cas#(b) command period, t ccd ) is minimum 1 clk. figure 24 read interrupted by read 3.6.2 read interrupted by a write to interrupt a burst read with a write command, a burst stop command must be asserted to avoid data contention on the i/o bus by placing the dq's (output drivers) in a high impedance state at least one clock cycle before the write command is initiated (last output to write command latency). to insure that the dqs are tri-stated one cycle before the write operation begins, the burst stop command must be applied at least 3 clock cycles for cl = 2, at least 4 clock cycles for cl = 3 or at leas t 5 clock cycles for cl = 4 before the write command. figure 25 read interrupted by write clk read a dqsx dqx d-out a0 command read b nop nop nop nop d-out a1 d-out b1 t ccd burst length = 4 cl = 2 d-out b0 d-out b3 d-out b2 clk read dqsx dqx d-out 0 command bst nop nop write nop d-out 1 d-in 1 burst length = 4 cl = 2 d-in 0 d-in 3 d-in 2 burst stop to write command latency nop nop burst stop latency = cl
data sheet 33 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set 3.6.3 read interr upted by a precharge a burst read operation can be interrupted by a precharge of the same bank. the read command to precharge time is minimum 1 clock cycle. the precharge command di sables the data output depending on the cas latency. once the last data bit has been outputted, the output buffers are tristated. a new bank activate command may be issued to the same bank after t rp . figure 26 read interrupted by precharge 3.6.4 write interrupted by a write a burst write can be interrupted before completion of the burst by a new write command. the minimum distance between two different write commands is one clock cycle. when the previous burst is interrupted, the remaining addresses are overridden by the new ad dress and data will be written into th e device until the programmed burst length is satisfied. the write to write interval (cas a to cas b command period) is defined by the parameter t ccd . figure 27 write interrupted by write clk read dqsx dqx d-out 0 command nop pre nop nop act d-out 1 burst length = 8 cl = 2 nop precharge latency = cl d-out 2 d-out 3 t rp first possible act command clk write a dqsx dqx d-in a0 command write b nop nop nop d-in a1 d-in b1 t ccd burst length = 4 d-in b0 d-in b3 d-in b2
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 34 v1.7, 2003-07 3.6.5 write interrupted by a read a burst write can be interrupted by a read command sent to any bank. the dqs must be in the high impedance state at least one clock cycle before the data of the interrupting read appears on the outputs to avoid data contention. before the read command is registered, any re sidual data from the burst write cycle must be masked by dmx. data that is presented on the dq pins before the read command is initiated, will actu ally be written to the memory. figure 28 write interrupted by read 3.6.6 write interrupted by a precharge a burst write operation can be interrupted before completion of the burst by a precharge of the same bank. random column access is allowed. a write recovery time ( t wr ) is required from the last data to precharge command. when precharge command is asserted, any residual data from the burst write cycle must be masked by dmx. nop d-in 2 clk write dqsx dqx d-in 0 command t wtr dmx cl = 2 nop nop read nop nop d-in 1 d-in 3 t dqss d-out 0 d-out 1 last valid data data must be masked burst length = 8 cl = 2 data is masked by read d-in 4 d-in 5
data sheet 35 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set figure 29 write interrupted by precharge 3.7 operations and functions table 9 command overview operation code cke n-1 cke n cs# ras# cas# we# ba0 ba1 a8 a0-7 a9-11 device deselect desel h x h x x x x x x x no operation nop h x l h h h x x x x mode register setup mrs h x l l l l 0 0 opcode extended mode register setup mrs hxllll10opcode bank activate act h x l l h h ba ba row address read read h x l l h h ba ba l col. read with auto precharge reada h x l h l h ba ba h col. write command write h x l l h h ba ba l col. write command with auto precharge writea h x l h l h ba ba h col. burst stop bst h x l h h l x x x x precharge single bank pre h x l l h l ba ba l x precharge all banks preal h x l l h l x x h x auto refresh aref h h l l l h x x x x self refresh entry srefen h l l l l h x x x x self refresh exit srefex l l h h h l x h x h x h x x x x x x x x d-in 2 clk write bank a dqsx dqx d-in 0 command t wr dmx nop nop nop pre write bank b nop d-in 1 d-in 3 t dqss nop d-in 0 d-in 1 last valid data data must be masked data is masked by precharge burst length = 8 t dqss d-in 4 d-in 5
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 36 v1.7, 2003-07 note: the power down mode entry command is illegal during burst read or burst write operations. 3.8 function truth tables table 10 lists all abbreviations used in table 11 and table 12 . power down mode entry (note) pwdnen h h l l h l x h x h x h x x x x x x x x power down mode exit pwdnex l h h l x valid x valid x valid xxxx table 10 abbreviations h high level l low level xdon?t care v valid data input ra row address ba bank address pa precharge all nop no operation ca column address ax address line x table 11 function truth table i current state command address action notes idle desel x nop 3) 1) 3) nop x nop 3) 2) 3) bst x nop 3) read / reada ba,ca,a8 illegal 1) 4) 1) write / writea ba,ca,a8 illegal 1) 1) act ba, ra bank active pre / preal ba, a8 nop aref / sref x auto-refr esh or self-refresh 4) 5) 4) mrs / emrs op-code mode register set or extended mode register set table 9 command overview (cont?d) operation code cke n-1 cke n cs# ras# cas# we# ba0 ba1 a8 a0-7 a9-11
data sheet 37 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set row active desel x nop nop x nop bst x nop read / reada ba, ca, a8 begin read, determine auto precharge 9) 6) 9) write / writea ba, ca, a8 begin wr ite, determine auto precharge 9) 9) act ba, ra illegal 1), 5) 1), 5) pre / preal ba, a8 prec harge / precharge all 6) 7) 6) aref / sref x illegal mrs / emrs op-code illegal read desel x continue burst to end nop x continue burst to end bst x terminate burst read / reada ba, ca, a8 term inate burst, begin new read, determine auto-prechgarge 7) 8) 7) write / writea ba, ca, a8 illegal 2), 7) 9) 2), 7) act ba, ra illegal 1) 1) pre / preal ba ,a8 terminate burst / precharge aref / sref x illegal mrs / emrs op-code illegal read with auto precharge desel x continue burst to end, precharge nop x continue burst to end, precharge bst ba illegal read / reada ba, ca, a8 illegal write / writea ba, ca, a8 illegal act ba, ra illegal 1) 1) pre / preal ba ,a8 illegal 1) 1) aref / sref x illegal mrs / emrs op-code illegal write desel x continue burst to end nop x continue burst to end bst x illegal read / reada ba, ca, a8 terminat e burst, begin read, determine auto-precharge. 7), 8) 7), 8) write / writea ba, ca, a8 termin ate burst, begin new write, determine auto-precharge 2), 7) 2), 7) act ba, ra illegal 1) 1) pre / preal ba ,a8 terminate burst , precharge 8) 8) aref / sref x illegal mrs / emrs op-code illegal table 11 function truth table i (cont?d) current state command address action notes
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 38 v1.7, 2003-07 write with autoprecharge desel x continue burst to end, precharge nop x continue burst to end, precharge bst x illegal read / reada ba, ca, a8 illegal write / writea ba, ca, a8 illegal act ba, ra illegal 1) 1) pre / preal ba ,a8 illegal 1) 1) aref / sref x illegal mrs / emrs op-code illegal row activating desel x nop ( row active after t rcd ) nop x nop ( row active after t rcd ) bst x nop ( row active after t rcd ) read / reada ba, ca, a8 illegal 1), 9) 1), 9) write / writea ba, ca, a8 illegal 1), 9) 1), 9) act ba, ra illegal 1), 5) 1), 5) pre / preal ba ,a8 illegal 1), 6) 1), 6) aref / sref x illegal mrs / emrs op-code illegal precharge desel x nop ( row idle after t rp ) nop x nop ( row idle after t rp ) bst x nop ( row idle after t rp ) read / reada ba, ca, a8 illegal 1) 1) write / writea ba, ca, a8 illegal 1) 1) act ba, ra illegal 1) 1) pre / preal ba ,a8 nop ( row idle after t rp ) 1) 1) aref / sref x illegal mrs / emrs op-code illegal write recovering desel x nop (row active after t wr ) nop x nop (row active after t wr ) bst x nop (row active after t wr ) read / reada ba, ca, a8 begin re ad, determine auto-prechgarge 2) 2) write / writea ba, ca, a8 begin wr ite, determine auto-prechgarge act ba, ra illegal 2) 2) pre / preal ba ,a8 illegal 1),10) aref / sref x illegal mrs / emrs op-code illegal table 11 function truth table i (cont?d) current state command address action notes
data sheet 39 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set note: all entries assume the cke was high during the preceding clock cycle write recovering with auto- precharge desel x nop (precharge after t wr ) nop x nop (precharge after t wr ) bst x nop (precharge after t wr ) read / reada ba, ca, a8 illegal 1), 2) write / writea ba, ca, a8 illegal 1) act ba, ra illegal 1) pre / preal ba ,a8 illegal 1) aref / sref x illegal mrs / emrs op-code illegal refresh desel x nop (idle after t rc ) nop x nop (idle after t rc ) bst x nop (idle after t rc ) read / reada ba, ca, a8 illegal write / writea ba, ca, a8 illegal act ba, ra illegal 11) pre / preal ba ,a8 illegal aref / sref x illegal mrs / emrs op-code illegal (extended mode register set) desel x nop (idle after two clocks) nop x nop (idle after two clocks) bst x nop (idle after two clocks) read / reada ba, ca, a8 illegal write / writea ba, ca, a8 illegal act ba, ra illegal pre / preal ba ,a8 illegal aref / sref x illegal mrs / emrs op-code illegal 1) illegal to bank specified states; function may be legal in t he bank indicated by bax, depending on the state of that bank 2) must satisfy bus contention, bus turn around, write recovery requirements. 3) if both banks are idle, and cke is inactive, the device will enter power down mode. all input buffers except cke, clk and clk# will be disabled. 4) if both banks are idle, and cke is deactivated coinci dentally with an autorefresh command, the device will enter selfrefresh mode. all input buffers except cke will be disabled. 5) illegal, if t rrd is not satisfied. 6) illegal, if t ras is not satisfied. 7) must satisfy burst interrupt condition. 8) must mask two preceding dat a bits with the dm pin. 9) illegal, if t rcd is not satisfied. 10) illegal, if t wr is not satisfied. 11) illegal, if t rc is not satisfied. table 11 function truth table i (cont?d) current state command address action notes
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set data sheet 40 v1.7, 2003-07 table 12 function truth table for cke current state cke n-1 cke n cs# ras # cas # we# address action notes self refresh hxxxxxx invalid 1) 1) cke low-to-high transition re-enables inputs asynchronously. a minimum setup time to clk must be satisfied before any commands other than exit are executed. l hhxxxx exit self-refresh ( idle after t srx ) 1) l hl hhhx exit self-refresh ( idle after t srx ) 1) l hl hhxx illegal 1) l hl hhxx illegal 1) lhlllxx illegal 1) l l xxxxx nop ( maintain self refresh) 1) power down hxxxxxx invalid l hxxxxx exit power down ( idle after t pdex ) l l xxxxx nop ( maintain power down) all banks idle hhxxxxx refer to function truth table 2) 2) power down can be entered when all banks are idle (banks can be active or precharged) h l l l l h x enter self refresh 3) 3) self refresh can be entered only from the precharge / idle state. hl hxxxx enter power-down 2) hl l hhhx enter power-down 2) hl l hhl x illegal 2) h l l h l x x illegal 2) hl l l xxx illegal 2) l xxxxxx refer to power down in this table all other states hhxxxxx refer to funtion truth table
data sheet 41 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] register set 3.9 ddr sgram simpli fied state diagram figure 30 ddr sgram simplified state diagram row active idle act auto refresh aref mode register set mrs self refresh srefen srefex power down ckel ckeh read reada read reada write read writea pre charge pre pre pre reada writea power on pre ckel ckeh automatic sequence command sequence write reada bst writea
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics data sheet 42 v1.7, 2003-07 4 electrical characteristics attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 13 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?0.5 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?0.5 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?0.5 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg ?55 ? +150 c? power dissipation p d ?1.4?w ? short circuit output current i out ?50?ma? table 14 power & dc operation conditions parameter symbol values unit notes 1) min. typ. max. power supply voltage v dd 2.38 2.5 2.63 v l3.6, l4.5 2) v dd 2.38 2.5 2.63 v ?3.6, ?4.5, ?5 2) v dd 2.5 ? 2.9 v ?3.6, l3.6 2)3) v dd 2.5 ? 2.9 v ?3, ?3.3 2) power supply voltage for i/o buffer v ddq 2.38 2.5 2.63 v 2) 4) reference voltage v ref 0.49 v ddq 1.25 0.51 v ddq v 5) 6) termination voltage v t t v ref - 0.04 v ref v ref + 0.04 v 7) input leakage current i il ?5 ? 5 a ? clk input leakage current i ilc ?5 ? 5 a ? output leakage current i ol ?5 ? 5 a ? input logic high voltage, dc v ih v ref + 0.15 ? v ddq + 0.3 v 8) input logic low voltage, dc v il v ssq - 0.3 ? v ref - 0.15 v 9) output levels: matched impedance mode 2.5v high current at v out = v ddq -0,373v i oh ?5 ? ? ma ? low current at v out = 0.373v i ol 5??ma? output levels: sstl2 weak mode 2.5v high current at v out = v ddq ? 0,373v i oh ?5 ? ? ma ? low current at v out = 0.373v i ol 5??ma?
data sheet 43 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics figure 31 output test circuit 1) t a = 0 to 70 c; v ss = 0 v 2) under all conditions, v ddq must be less than or equal to v dd 3) the speed sorts l3.6 and ?3.6 support both v dd modes: 2.5v 5% and 2.5v ? 2.9v 4) v ddq = 2.5 v -/+5% 5) typically the value of v ref is expected to be 0.5 * v ddq of the transmitting device. v ref is expected to track variations in v ddq 6) peak to peak ac noise on v ref may not exceed 2% v ref (dc) 7) v tt of the transmitting device must track v ref of the receiving device 8) overshoots of v ih must be limited to a voltage < ( v ddq + 1.5 v) and a pulse width < 0.33 of the clock pulse 9) undershoots of v il must be limited to a voltage > -1.5 v and a pulse width < 0.33 of the clock pulse table 15 ac operation conditions parameter symbol values unit notes min. typ. max. input logic high voltage v ih v ref + 0.50 ? v ddq + 0.3 v l3.6, l4.5 v ref + 0.60 ? v ddq + 0.3 v ?5.0 v ref + 0.50 ? v ddq + 0.3 v ?3, ?3.3, ?3.6, ?4.5 input logic low voltage v il v ssq - 0.3 ? v ref - 0.50 v l3.6, l4.5 v ssq - 0.3 ? v ref - 0.60 v ?5.0 v ssq - 0.3 ? v ref - 0.50 v ?3, ?3.3, ?3.6, ?4.5 clock differential input voltage (clk/clk ) v id 1.2 ? v ddq + 0.6 v l4.5 1.0 ? v ddq + 0.6 v l3.6 1.2 ? v ddq + 0.6 v ?4.5, ?5.0 1.0 ? v ddq + 0.6 v ?3, ?3.3, ?3.6, ?4.5 clock input crossing point (clk/clk ) v ix v ref - 0.2 v ref v ref + 0.2 v ? i/o reference voltage v ref 0.49 v ddq ?0.51 v ddq v? input slew rate r i 1.0 ? ? v/ns ? table 16 pin capacitances pin min. max. unit a11.. a0, ba1, ba0, cke, cs , cas , ras , we 1.0 2.5 pf clk, clk 1.0 2.5 pf 15 pf dq, dqs + vtt = 0.5xv ddq 50 ohm test point
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics data sheet 44 v1.7, 2003-07 dq0.. dq31, dqs0 .. dqs3 1.0 3.0 pf dm0.. dm3 1.0 3.0 pf table 17 timing parameters for speed sorts ?3, ?3.3, ?3.6, ?4.5, and ?5 part number extension ?3 ?3.3 ?3.6 ?4.5 ?5 unit note 1) interface mim mim mim wm/mim wm/mim ? 2) parameter symbol min. max. min. max. min. max. min. max. min. max. ? ? clock and clock enable clock cycle time t ck 3.0 5.0 3.3 5.0 3.6 5.0 4.5 5.5 5.0 5.5 ns cl = 4 t ck 4.0 5.0 4.0 5.0 4.2 5.0 4.5 5.5 5.0 5.5 ns cl = 3 system frequency f ck 200 333 200 300 200 278 183 222 183 200 mhz cl = 4 f ck 200 250 200 250 200 238 183 222 183 200 mhz cl = 3 clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck ? clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck ? minimum clock half period t hp t ch , t cl ? t ch , t cl ? t ch , t cl ? t ch , t cl ? t ch , t cl ?t ck ? command and address setup and hold times address and command input setup time t is 0.65 ? 0.65 ? 0.75 ? 1.0 ? 1.0 ? ns ? address and command input hold time t ih 0.65 ? 0.65 ? 0.75 ? 1.0 ? 1.0 ? ns ? common parameters row cycle time t rc 39 ? 42.9 ? 46.8 ? 54 ? 60 ? ns ? row cycle time in auto refresh t rfc 45 ? 49.5 ? 54 ? 63 ? 70 ? ns ? row active time t ras 27 15.7k 29.7 15.7k 32.4 15.7k 36 15.7k 40 15.7k ns ? active to read with auto precharge command t rap t ras (min.) - (burst length * t ck /2) ns ? row precharge time t rp 12 ? 13.2 ? 14.4 ? 18 ? 20 ? ns ? activate(a) to activate(b) command period t rrd 9.0 ? 9.0 ? 9.0 ? 9.0 ? 9.0 ? ns ? cas (a) to cas (b) command period t ccd 1?1?1 ?1?1?t ck ? last data in to active ( t wr + t rp ) t dal 6?6?6 ?6?6?t ck ? table 16 pin capacitances pin min. max. unit
data sheet 45 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics read cycle timing parameters for data and data strobe data access time from clock t ac -0.5 +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 +0.7 -0.7 +0.7 ns ? dqs edge to clock edge skew t dqsck -0.5 +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 +0.7 -0.7 +0.7 ns ? dqs read preamble t rpre 0.7 0.9 0.7 0.9 0.7 0.9 0.7 0.9 0.7 0.9 t ck ? dqs read postamble t rpst 0.8 1.1 0.8 1.1 0.8 1.1 0.8 1.1 0.8 1.1 t ck ? row to column delay time for reads t rcddc 4?4?4 ?4?4?t ck ? dqs edge to output data edge skew t dqsq ? +0.3 ? +0.3 ? +0.33 ? +0.45 ? +0.5 ns ? data hold skew factor t qhs ? 0.33 ? 0.33 ? 0.36 ? 0.45 ? 0.5 ns ? data output hold time from dqs t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ns ? write cycle timing parameters for data and data strobe row to column delay time for writes t rcdwr 2?2?2 ?2?2? t ck ? clock to rising edge dqs (write latency) t dqss 0.75 1.1 0.75 1.1 0.75 1.1 0.75 1.25 0.75 1.25 t ck ? data-in to dqs setup time t qdqss 0.40 ? 0.40 ? 0.40 ? 0.6 ? 0.6 ? ns ? data-in to dqs hold time t qdqsh 0.40 ? 0.40 ? 0.40 ? 0.6 ? 0.6 ? ns ? data mask to dqs setup time t dmdqss 0.40 ? 0.40 ? 0.40 ? 0.6 ? 0.6 ? ns ? data mask to dqs hold time t dmdqsh 0.40 ? 0.40 ? 0.40 ? 0.6 ? 0.6 ? ns ? clock to dqs write preamb. setup time t wpres 0?0?0 ?0?0? t ck ? clock to dqs write preamble hold time t wpreh 0.25 ? 0.25 ? 0.25 ? 0.25 ? 0.25 ? t ck ? dqs write postamble hold time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck ? write recovery time t wr 2?2?2 ?2?2? t ck 3) table 17 timing parameters for speed sorts ?3, ?3.3, ?3.6, ?4.5, and ?5 (cont?d) part number extension ?3 ?3.3 ?3.6 ?4.5 ?5 unit note 1) interface mim mim mim wm/mim wm/mim ? 2) parameter symbol min. max. min. max. min. max. min. max. min. max. ? ?
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics data sheet 46 v1.7, 2003-07 internal write to read command delay t wtr 1?1?1 ?1?1? t ck ? write dqs high level width t dqsh 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 t ck ? write dqs low level width t dqsl 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 t ck ? refresh cycle refresh period (4096 cycles) t ref ?32?32?32?32?32ms? average periodic refresh interval t refc ? 7.8 ? 7.8 ? 7.8 ? 7.8 ? 7.8 us ? refresh to refresh command interval t refc ? 15.7 ? 15.7 ? 15.7 ? 15.7 ? 15.7 s? mode setup, power down & self refresh mode register set cycle time t mrd 2?2?2 ?2?2? t ck ? self refresh exit time t srex 200 ? 200 ? 200 ? 200 ? 200 ? t ck ? power down exit time t pdex 2* t ck + t is ? 2* t ck + t is ? 2* t ck + t is ? 1* t ck + t is ? 1* t ck + t is ?ns? 1) all parameters only valid for: t a = 0 to 70 c; v ss =0v; 2.5v < v dd < 2.9 v for ?3 and ?3.3; 2.375 v < v dd < 2.9 v for ?3.6; v dd =2.5v 0.125 v for ?4.5 and ?5; v ddq =2.5v 0.125 v 2) maximum clock rate is only guaranteed with the specified in terface. the sstl2-weak mode interface is limited to a maximum speed of 250mhz. 3) the write recovery time starts at the first rising edge of clock after the last valid (falling) dqs edge of the slowest dqs signal. table 18 timing parameters for speed sorts l3.6 and l4.5 part number extension l3.6 l4.5 unit note 1) interface mim wm/mim ? 2) parameter symbol min. max. min. max. ? ? clock and clock enable clock cycle time 3.6 6.0 4.5 6.0 ns cl = 4 t ck 4.2 10 4.5 10 ns cl = 3 system frequency f ck 166 278 166 222 mhz cl = 4 f ck 100 238 100 222 mhz cl = 3 clock high level width t ch 0.45 0.55 0.45 0.55 t ck ? table 17 timing parameters for speed sorts ?3, ?3.3, ?3.6, ?4.5, and ?5 (cont?d) part number extension ?3 ?3.3 ?3.6 ?4.5 ?5 unit note 1) interface mim mim mim wm/mim wm/mim ? 2) parameter symbol min. max. min. max. min. max. min. max. min. max. ? ?
data sheet 47 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics clock low level width t cl 0.45 0.55 0.45 0.55 t ck ? minimum clock half period t hp t ch , t cl ? t ch , t cl ? t ck ? command and address setup and hold times address and command input setup time t is 0.75 ? 1.0 ? ns ? address and command input hold time t ih 0.75 ? 1.0 ? ns ? common parameters row cycle time t rc 46.8 ? 54 ? ns ? row cycle time in auto refresh t rfc 54 ? 63 ? ns ? row active time t ras 32.4 15.7k 36 15.7k ns ? active to read with auto precharge command t rap t ras (min.) - (burst length * t ck /2) ns ? row precharge time t rp 14.4 ? 18 ? ns ? activate(a) to activate(b) command period t rrd 9.0 ? 9.0 ? ns ? cas (a) to cas (b) command period t ccd 1 ? 1 ? t ck ? last data in to active ( t wr + t rp ) t dal 6 ? 6 ? t ck ? read cycle timing parameters for data and data strobe data access time from clock t ac -0.55 +0.55 -0.7 +0.7 ns ? dqs edge to clock edge skew t dqsck -0.55 +0.55 -0.7 +0.7 ns ? dqs read preamble t rpre 0.7 0.9 0.7 0.9 t ck ? dqs read postamble t rpst 0.8 1.1 0.8 1.1 t ck ? row to column delay time for reads t rcddc 4?4? t ck ? dqs edge to output data edge skew t dqsq ? +0.33 ? +0.45 ns ? data hold skew factor t qhs ? 0.36 ? 0.45 ns ? data output hold time from dqs t qh t hp ? t qhs t hp ? t qhs ns ? write cycle timing parameters for data and data strobe row to column delay time for writes t rcdwr 2?2? t ck ? clock to rising edge dqs (write latency) t dqss 0.75 1.1 0.75 1.25 t ck ? data-in to dqs setup time t qdqss 0.40 ? 0.6 ? ns ? data-in to dqs hold time t qdqsh 0.40 ? 0.6 ? ns ? data mask to dqs setup time t dmdqss 0.40 ? 0.6 ? ns ? data mask to dqs hold time t dmdqsh 0.40 ? 0.6 ? ns ? clock to dqs write preamb. setup time t wpres 0?0? t ck ? clock to dqs write preamble hold time t wpreh 0.25 ? 0.25 ? t ck ? dqs write postamble hold time t wpst 0.4 0.6 0.4 0.6 t ck ? write recovery time t wr 2?2? t ck 3) table 18 timing parameters for speed sorts l3.6 and l4.5 (cont?d) part number extension l3.6 l4.5 unit note 1) interface mim wm/mim ? 2) parameter symbol min. max. min. max. ? ?
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics data sheet 48 v1.7, 2003-07 internal write to read command delay t wtr 1?1? t ck ? write dqs high level width t dqsh 0.35 0.65 0.35 0.65 t ck ? write dqs low level width t dqsl 0.35 0.65 0.35 0.65 t ck ? refresh cycle refresh period (4096 cycles) t ref ?32?32ms? average periodic refresh interval t refc ? 7.8 ? 7.8 us ? refresh to refresh command interval t refc ? 15.7? 15.7us ? mode setup, power down & self refresh mode register set cycle time t mrd 2?2? t ck ? self refresh exit time t srex 200 ? 200 ? t ck ? power down exit time t pdex 2* t ck + t is ? 1* t ck + t is ?ns? 1) all parameters only valid for: t a = 0 to 70 c; v ss = 0 v; 2.375 v < v dd < 2.9 v for l3.6; v dd =2.5v 0.125 v for l4.5; v ddq =2.5v 0.125 v 2) maximum clock rate is only guarantee d with the specified interfac e. the sstl2-weak mode in terface is limited to a maximum speed of 250mhz. 3) the write recovery time starts at the first rising edge of clock after the last valid (falli ng) dqs edge of the slowest dqs signal. table 19 HYB25D128323C?3 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 333 mhz / 3.0 ns 4 13 15 9 4 2 3 6 4 2 t ck 300 mhz / 3.3 ns 4 13 15 9 4 2 3 6 4 2 t ck 278 mhz / 3.6 ns 4 13 15 9 4 2 3 6 4 2 t ck 250 mhz / 4.0 ns 3 12 14 8 4 2 3 6 3 2 t ck 222 mhz / 4.5 ns 3 10 12 7 3 2 2 5 3 2 t ck 200 mhz / 5.0 ns 3 9 11 6 3 2 2 5 3 2 t ck table 18 timing parameters for speed sorts l3.6 and l4.5 (cont?d) part number extension l3.6 l4.5 unit note 1) interface mim wm/mim ? 2) parameter symbol min. max. min. max. ? ?
data sheet 49 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics table 20 HYB25D128323C?3.3 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 300 mhz / 3.3 ns 4 13 15 9 4 2 3 6 4 2 t ck 278 mhz / 3.6 ns 4 13 15 9 4 2 3 6 4 2 t ck 250 mhz / 4.0 ns 3 12 14 8 4 2 3 6 3 2 t ck 222 mhz / 4.5 ns 3 10 12 7 3 2 2 5 3 2 t ck 200 mhz / 5.0 ns 3 9 11 6 3 2 2 5 3 2 t ck table 21 HYB25D128323C?3.6 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 278 mhz / 3.6 ns 4 13 15 9 4 2 3 6 4 2 t ck 250 mhz / 4.0 ns 4 13 15 9 4 2 3 6 4 2 t ck 222 mhz / 4.5 ns 3 12 14 8 4 2 2 6 4 2 t ck 200 mhz / 5.0 ns 3 10 12 7 3 2 2 5 3 2 t ck table 22 HYB25D128323C?4.5 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 222 mhz / 4.5 ns 3 12 14 8 4 2 2 6 4 2 t ck 200 mhz / 5.0 ns 3 12 14 8 4 2 2 6 4 2 t ck 183 mhz / 5.5 ns 3 12 14 8 4 2 2 6 4 2 t ck table 23 HYB25D128323C?5 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 200 mhz / 5.0 ns 3 12 14 8 4 2 2 6 4 2 t ck 183 mhz / 5.5 ns 3 12 14 8 4 2 2 6 4 2 t ck
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics data sheet 50 v1.7, 2003-07 table 24 HYB25D128323Cl3.6 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 278 mhz / 3.6 ns 4 13 15 9 4 2 3 6 4 2 t ck 250 mhz / 4.0 ns 4 13 15 9 4 2 3 6 4 2 t ck 222 mhz / 4.5 ns 3 12 14 8 4 2 2 6 4 2 t ck 200 mhz / 5.0 ns 3 10 12 7 3 2 2 5 3 2 t ck 166 mhz / 6.0 ns 3 9 11 6 3 2 2 5 3 2 t ck table 25 HYB25D128323Cl4.5 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t dal t rcdrd t rcdwr units 222 mhz / 4.5 ns 3 12 14 8 4 2 2 6 4 2 t ck 200 mhz / 5.0 ns 3 12 14 8 4 2 2 6 4 2 t ck 183 mhz / 5.5 ns 3 12 14 8 4 2 2 6 4 2 t ck 166 mhz / 6.0 ns 3 10 12 7 3 2 2 5 3 2 t ck 143 mhz / 7.0 ns 3 9 11 6 3 2 2 5 3 2 t ck table 26 operating currents parameter & test condition symbol ?3 ?3.3 ?3.6 ?4.5 ?5.0 l3.6 l4.5 unit notes max. typ. typ. operating current: one bank; active-precharge; t rc = t rc(min.) ; t ck = t ck(min.) ; dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 200 190 180 160 150 ma 1) operating current: one bank; active-read-precharge; bl=4; cl=4; t rcddc =4* t ck ; t rc = t rc(min.) ; t ck = t ck(min.) ; i out = 0ma; address and control inputs changing once per clock cycle i dd1 230 220 110 190 180 ma precharge power-down standby current: all banks idle; power-down mode; t ck = t ck(min.) ; cke=low i dd2p 26 22 22 14 14 10 7 ma
data sheet 51 v1.7, 2003-07 HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] electrical characteristics idle standby current: cke=high; cs#=high (deselect); all banks idle; t ck = t ck(min.) ; address and control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm i dd2f 130 120 110 100 100 ma active power-down standby current: one bank active; power- down mode; cke=low; t ck = t ck(min.) ; i dd3p 65 60 55 50 50 ma active standby current: cs#=high; cke=high; one bank active; t rc = t rc(max.) ; t ck = t ck(min.) ; address and control inputs changing once per clock cycle; dq, dqs, and dm inputs changing twice per clock cycle i dd3n 130 120 110 100 100 ma operating current burst read: bl=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck(min.) ; iout=0ma; 50% of data changing on every transfer i dd4r 370 350 330 290 280 190 160 ma operating current burst write: bl=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck(min.) ; dq, dqs, and dm changing twice per clock cycle; 50% of data changing on every transfer i dd4w 370 350 330 290 280 200 175 ma auto refresh current: t rc = t rfc(min.) ; t ck = t ck(min.) i dd5 320 300 280 240 230 ma self refresh current: self refresh mode; cke<=0.2v; t ck = t ck(min.) i dd6 20 16 16 10 10 4 3 ma burst operating current 4 bank operation: four bank interleaving reads; bl=4; with auto precharge; t rc = t rc(min.) ; t ck = t ck(min.) ; address and control inputs change only during active, read, or write commands i dd7 430 400 370 320 300 ma 1) 1) measured with output open. table 26 operating currents (cont?d) parameter & test condition symbol ?3 ?3.3 ?3.6 ?4.5 ?5.0 l3.6 l4.5 unit notes max. typ. typ.
HYB25D128323C[-3/-3.3/-3. 6/-4.5/-5.0/l3.6/l4.5] 128 mbit ddr sgram [4m x 32] package outlines data sheet 52 v1.7, 2003-07 5 package outlines figure 32 package outlines module package the package is conforming with jedec mo-205 variation bd general tolerances according to iso 8015 the inner matrix of 4 4 balls is reserved for thermal contacts 11.1 10.9 11.1 10.9 0 . 1 0 all dimensions in mm. notation is or or typ 8.8 8.8 8.8 8.8 0.8 -- 0.8 -- - - 0.85 1.44 1.36 1.50 max min typ max min
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